ASCI Red Supercomputer (1996)

The ASCI Option Red Supercomputer

The ASCI Option Red Supercomputer is a Massively Parallel Processor (MPP) with a distributed memory Multiple-Instruction, Multiple Data (MIMD) architecture.

All aspects of this system are scalable including the aggregate communication bandwidth, the number of compute nodes, the amount of main memory, disk storage capacity and I/O bandwidth.

The Intel Pentium Pro processor is used on all the nodes in the ASCI option red supercomputer. The Intel Pentium Pro processor is both a CISC and a RISC chip. Its instruction set is essentially the same as that for the Pentium processor. At runtime, however, the CISC instructions are broken down into simpler, RISC instructions called micro-operations (or uops). The uops execute in a RISC core inside the Pentiumâ Pro processor with the order of execution dictated by the availability of data. This lets the CPU continue with productive work when other uops are waiting for data or functional units. This out of order execution is combined with sophisticated branch prediction and register renaming to provide what Intel calls, dynamic execution.

See the Table below for a technical description of the system.

. Information and photo courtesy of Sandia National Laboratories

 

Table 1: System parameters for the ASCI Option Red Supercomputer.

Compute Nodes

4,536

Service Nodes

32

Disk I/O Nodes

32

System Nodes (Boot)

2

Network Nodes (Ethernet, ATM)

10

System Footprint

1,600 Square Feet

Number of Cabinets

85

System RAM

594 Mbytes

Topology

38x32x2

Node to Node bandwidth - Bi-directional

800 Mbytes/sec

Bi-directional - Cross section Bandwidth

51.6 Gbytes/sec

Total number of Pentiumâ Pro Processors

9,216

Processor to Memory Bandwidth

533 Mbytes/sec

Compute Node Peak Performance

400 MFLOPS

System Peak Performance

1.8 TFLOPS

RAID I/O Bandwidth (per subsystem)

1.0 Gbytes/sec

RAID Storage (per subsystem)

1 Tbyte

 


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